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1/23 l6206 september 2003 n operating supply voltage from 8 to 52v n 5.6a output peak current (2.8a dc) n r ds(on) 0.3 w typ. value @ t j = 25 c n operating frequency up to 100khz n programmable high side overcurrent detection and protection n diagnostic output n paralleled operation n cross conduction protection n thermal shutdown n under voltage lockout n integrated fast free wheeling diodes typical applications n bipolar stepper motor n dual or quad dc motor description the l6206 is a dmos dual full bridge designed for motor control applications, realized in multipower- bcd technology, which combines isolated dmos power transistors with cmos and bipolar circuits on the same chip. available in powerdip24 (20+2+2), powerso36 and so24 (20+2+2) packages, the l6206 features thermal shutdown and a non-dissipa- tive overcurrent detection on the high side power mosfets plus a diagnostic output that can be easily used to implement the overcurrent protection. block diagram d99in1088a gate logic over current detection over current detection gate logic vcp vboot en a in1 a in2 a en b in1 b in2 b v boot 5v 10v vs a v s b out1 a out2 a out1 b out2 b sense a charge pump voltage regulator thermal protection v boot v boot 10v 10v bridge a bridge b sense b progcl b ocd b ocd a progcl a ocd a ocd b ordering numbers: l6206n (powerdip24) l6206pd (powerso36) l6206d (so24) powerdip24 (20+2+2) powerso36 so24 (20+2+2) dmos dual full bridge driver
l6206 2/23 absolute maximum ratings recommended operating conditions symbol parameter test conditions value unit v s supply voltage v sa = v sb = v s 60 v v od differential voltage between vs a , out1 a , out2 a , sense a and vs b , out1 b , out2 b , sense b v sa = v sb = v s = 60v; v sensea = v senseb = gnd 60 v ocd a ,ocd b ocd pins voltage range -0.3 to +10 v progcl a , progcl b progcl pins voltage range -0.3 to +7 v v boot bootstrap peak voltage v sa = v sb = v s v s + 10 v v in ,v en input and enable voltage range -0.3 to +7 v v sensea, v senseb voltage range at pins sense a and sense b -1 to +4 v i s(peak) pulsed supply current (for each v s pin), internally limited by the overcurrent protection v sa = v sb = v s ; t pulse < 1ms 7.1 a i s rms supply current (for each v s pin) v sa = v sb = v s 2.8 a t stg , t op storage and operating temperature range -40 to 150 c symbol parameter test conditions min max unit v s supply voltage v sa = v sb = v s 852v v od differential voltage between vs a , out1 a , out2 a , sense a and vs b , out1 b , out2 b , sense b v sa = v sb = v s ; v sensea = v senseb 52 v v sensea, v senseb voltage range at pins sense a and sense b (pulsed t w < t rr ) (dc) -6 -1 6 1 v v i out rms output current 2.8 a t j operating junction temperature -25 +125 c f sw switching frequency 100 khz
3/23 l6206 thermal data pin connections (top view) (5) the slug is internally connected to pins 1,18,19 and 36 (gnd pins). symbol description powerdip24 so24 powerso36 unit r th-j-pins maximumthermal resistance junction-pins 18 14 - c/w r th-j-case maximum thermal resistance junction-case - - 1 c/w r th-j-amb1 maximumthermal resistance junction-ambient 1 (1) mounted on a multi-layer fr4 pcb with a dissipating copper surface on the bottom side of 6 cm 2 (with a thickness of 35 m). 43 51 - c/w r th-j-amb1 maximum thermal resistance junction-ambient 2 (2) mounted on a multi-layer fr4 pcb with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 m). --35 c/w r th-j-amb1 maximumthermal resistance junction-ambient 3 (3) mounted on a multi-layer fr4 pcb with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 m), 16 via holes and a ground layer. --15 c/w r th-j-amb2 maximum thermal resistance junction-ambient 4 (4) mounted on a multi-layer fr4 pcb without any heat sinking surface on the board. 58 77 62 c/w powerdip24/so24 powerso36 (5) gnd gnd out1 b ocd b sense b in2 b in1 b 1 3 2 4 5 6 7 8 9 progcl b vboot en b out2 b vs b gnd gnd 19 18 17 16 15 13 14 d99in1089a 10 11 12 24 23 22 21 20 in1 a in2 a sense a ocd a out1 a vs a out2 a vcp en a progcl a gnd n.c. n.c. vs a ocd a out1 a n.c. n.c. n.c. n.c. n.c. out1 b ocd b n.c. vs b n.c. n.c. gnd 18 16 17 15 6 5 4 3 2 21 22 31 32 33 35 34 36 20 1 19 gnd gnd d99in1090a in1 a sense a in2 a sense b in2 b in1 b 9 8 7 28 29 30 progcl a progcl b 10 27 out2 a en a vcp en b out2 b vboot 14 12 11 23 25 26 n.c. n.c. 13 24
l6206 4/23 pin description package name type function so24/ powerdip24 powerso36 pin # pin # 1 10 in1 a logic input bridge a logic input 1. 2 11 in2 a logic input bridge a logic input 2. 3 12 sense a power supply bridge a source pin. this pin must be connected to power ground directly or through a sensing power resistor. 413ocd a open drain output bridge a overcurrent detection and thermal protection pin. an internal open drain transistor pulls to gnd when overcurrent on bridge a is detected or in case of thermal protection. 5 15 out1 a power output bridge a output 1. 6, 7, 18, 19 1, 18, 19, 36 gnd gnd signal ground terminals. in power dip and so packages, these pins are also used for heat dissipation toward the pcb. 8 22 out1 b power output bridge b output 1. 9 24 ocd b open drain output bridge b overcurrent detection and thermal protection pin. an internal open drain transistor pulls to gnd when overcurrent on bridge b is detected or in case of thermal protection. 10 25 sense b power supply bridge b source pin. this pin must be connected to power ground directly or through a sensing power resistor. 11 26 in1 b logic input bridge b input 1 12 27 in2 b logic input bridge b input 2 13 28 progcl b r pin bridge b overcurrent level programming. a resistor connected between this pin and ground sets the programmable current limiting value for the bridge b. by connecting this pin to ground the maximum current is set. this pin cannot be left non-connected. 14 29 en b logic input bridge b enable. low logic level switches off all power mosfets of bridge b. if not used, it has to be connected to +5v. 15 30 vboot supply voltage bootstrap voltage needed for driving the upper power mosfets of both bridge a and bridge b. 16 32 out2 b power output bridge b output 2. 17 33 vs b power supply bridge b power supply voltage. it must be connected to the supply voltage together with pin vs a . 20 4 vs a power supply bridge a power supply voltage. it must be connected to the supply voltage together with pin vs b . 21 5 out2 a power output bridge a output 2.
5/23 l6206 package name type function so24/ powerdip24 powerso36 pin # pin # 22 7 vcp output charge pump oscillator output. 23 8 en a logic input bridge a enable. low logic level switches off all power mosfets of bridge a. if not used, it has to be connected to +5v. 24 9 progcl a r pin bridge a overcurrent level programming. a resistor connected between this pin and ground sets the programmable current limiting value for the bridge a. by connecting this pin to ground the maximum current is set. this pin cannot be left non-connected. electrical characteristics (t amb = 25 c, v s = 48v, unless otherwise specified) symbol parameter test conditions min typ max unit v sth(on) turn-on threshold 6.6 7 7.4 v v sth(off) turn-off threshold 5.6 6 6.4 v i s quiescent supply current all bridges off; t j = -25c to 125c (6) 510ma t j(off) thermal shutdown temperature 165 c output dmos transistors r ds(on) high-side switch on resistance t j = 25 c 0.34 0.4 w t j =125 c (6) 0.53 0.59 w low-side switch on resistance t j = 25 c 0.28 0.34 w t j =125 c (6) 0.47 0.53 w i dss leakage current en = low; out = v s 2ma en = low; out = gnd -0.15 ma source drain diodes v sd forward on voltage i sd = 2.8a, en = low 1.15 1.3 v t rr reverse recovery time i f = 2.8a 300 ns t fr forward recovery time 200 ns logic input v il low level logic input voltage -0.3 0.8 v v ih high level logic input voltage 2 7 v i il low level logic input current gnd logic input voltage -10 a pin description (continued)
l6206 6/23 (6) tested at 25c in a restricted range and guaranteed by characterization. (7) see fig. 1. (8) see fig. 2. i ih high level logic input current 7v logic input voltage 10 a v th(on) turn-on input threshold 1.8 2.0 v v th(off) turn-off input threshold 0.8 1.3 v v th(hys) input threshold hysteresis 0.25 0.5 v switching characteristics t d(on)en enable to out turn on delay time (7) i load =2.8a, resistive load 100 250 400 ns t d(on)in input to out turn on delay time i load =2.8a, resistive load (dead time included) 1.6 s t rise output rise time (7) i load =2.8a, resistive load 40 250 ns t d(off)en enable to out turn off delay time (7) i load =2.8a, resistive load 300 550 800 ns t d(off)in input to out turn off delay time i load =2.8a, resistive load 600 ns t fa ll output fall time (7) i load =2.8a, resistive load 40 250 ns t dt dead time protection 0.5 1 s f cp charge pump frequency -25c 7/23 l6206 figure 1. switching characteristic definition figure 2. overcurrent detection timing definition v th(on) v th(off) 90% 10% en i out t t t fall t d(off)en t rise t d(on)en d01in1316 ocd threshold 90% 10% i out v ocd t t t ocd(off) t ocd(on) d01in1222
l6206 8/23 circuit description power stages and charge pump the l6206 integrates two independent power mos full bridges. each power mos has an rd- son=0.3ohm (typical value @ 25c), with intrinsic fast freewheeling diode. cross conduction protection is achieved using a dead time (td = 1 m s typical) be- tween the switch off and switch on of two power mos in one leg of a bridge. using n channel power mos for the upper transis- tors in the bridge requires a gate drive voltage above the power supply voltage. the bootstrapped (vboot) supply is obtained through an internal oscillator and few external components to realize a charge pump circuit as shown in figure 3. the oscillator output (vcp) is a square wave at 600khz (typical) with 10v amplitude. recommended values/part numbers for the charge pump circuit are shown in table1. table 1. charge pump external components values figure 3. charge pump circuit logic inputs pins in1 a , in2 a , in1 b , in2 b , en a and en b are ttl/ cmos and uc compatible logic inputs. the internal structure is shown in fig. 4. typical value for turn-on and turn-off thresholds are respectively vthon=1.8v and vthoff = 1.3v. pins en a and en b are commonly used to implement overcurrent and thermal protection by connecting them respectively to the outputs ocd a and ocd b , which are open-drain outputs. if that type of connec- tion is chosen, some care needs to be taken in driving these pins. two configurations are shown in fig. 5 and fig. 6. if driven by an open drain (collector) struc- ture, a pull-up resistor r en and a capacitor c en are connected as shown in fig. 5. if the driver is a stan- dard push-pull structure the resistor r en and the ca- pacitor c en are connected as shown in fig. 6. the resistor r en should be chosen in the range from 2.2k w to 180k w . recommended values for r en and c en are respectively 100k w and 5.6nf. more infor- mation on selecting the values is found in the over- current protection section. figure 4. logic inputs internal structure figure 5. en a and en b pins open collector driving figure 6. en a and en b pins push-pull driving truth table x = don't care high z = high impedance output c boot 220nf c p 10nf r p 100 w d1 1n4148 d2 1n4148 d2 c boot d1 r p c p v s vs a vcp vboot vs b d01in1328 inputs outputs en in1 in2 out1 out2 l x x high z high z h l l gnd gnd h h l vs gnd hlhgndvs hhhvsvs 5v d01in1329 esd protection 5v 5v open collector output r en c en en a or en b ocd a or ocd b d02in135 5 5v push-pull output r en c en en a or en b d02in135 6 ocd a or ocd b
9/23 l6206 non-dissipative overcurrent detection and protection in addition to the pwm current control, an overcurrent detection circuit (ocd) is integrated. this circuit can be used to provides protection against a short circuit to ground or between two phases of the bridge as well as a roughly regulation of the load current. with this internal over current detection, the external current sense resis- tor normally used and its associated power dissipation are eliminated. fig. 7 shows a simplified schematic of the overcurrent detection circuit for the bridge a. bridge b is provided of an analogous circuit. to implement the over current detection, a sensing element that delivers a small but precise fraction of the out- put current is implemented with each high side power mos. since this current is a small fraction of the output current there is very little additional power dissipation. this current is compared with an internal reference cur- rent i ref . when the output current reaches the detection threshold isover the ocd comparator signals a fault condition. when a fault condition is detected, an internal open drain mos with a pull down capability of 4ma connected to ocd pin is turned on. fig. 8 shows the ocd operation. this signal can be used to regulate the output current simply by connecting the ocd pin to en pin and adding an external r-c as shown in fig.7. the off time before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. i ref and, therefore, the output current detection threshold are selectable by r cl value, following the equations: C isover = 5.6a 30% at -25c < t j < 125c if r cl = 0 w (progcl connected to gnd) C isover = 10% at -25c < t j < 125c if 5k w < r cl < 40k w fig. 9 shows the output current protection threshold versus r cl value in the range 5k w to 40k w . the disable time t disable before recovering normal operation can be easily programmed by means of the accu- rate thresholds of the logic inputs. it is affected whether by c en and r en values and its magnitude is reported in figure 10. the delay time t delay before turning off the bridge when an overcurrent has been detected depends only by c en value. its magnitude is reported in figure 11. c en is also used for providing immunity to pin en against fast transient noises. therefore the value of c en should be chosen as big as possible according to the maximum tolerable delay time and the r en value should be chosen according to the desired disable time. the resistor r en should be chosen in the range from 2.2k w to 180k w . recommended values for r en and c en are respectively 100k w and 5.6nf that allow obtaining 200 m s disable time. 22100 r cl ----------------
l6206 10/23 figure 7. overcurrent protection simplified schematic figure 8. overcurrent protection waveforms + over temperature i ref i ref (i 1a +i 2a ) / n i 1a / n power sense 1 cell power sense 1 cell power dmos n cells power dmos n cells high side dmoss of the bridge a out1 a out2 a vs a i 1a i 2a i 2a / n ocd comparator to gate logic internal open-drain r ds(on) 40 w typ. c ena r ena r cla . en a ocd a progcl a, +5v 1.2v - + m c or logic d02in1354 i sover i out v th(on) v th(off) v en(low) v dd t ocd(on) t d(on)en t en(fall) t en(rise) t disable t delay t ocd(off) t d(off)en v en bridge on off ocd on off d02in1400
11/23 l6206 figure 9. output current protection threshold versus r cl value figure 10. t disable versus c en and r en (v dd = 5v). 5k 10k 15k 20k 25k 30k 35k 40k 0 0.5 1 1.5 2 2.5 3 3.5 5 r cl [ w ] 4 4.5 i sover [a] 1 10 100 1 10 100 1 . 10 3 c en [nf] t disable [s] r en = 220 k w r en = 100 k w r en = 47 k w r en = 33 k w r en = 10 k w 1 10 100 1 10 100 1 . 10 3 c en [nf] t disable [s] r en = 220 k w r en = 100 k w r en = 47 k w r en = 33 k w r en = 10 k w
l6206 12/23 figure 11. t delay versus c en (v dd = 5v). thermal protection in addition to the ovecurrent detection, the l6206 integrates a thermal protection for preventing the device destruction in case of junction over temperature. it works sensing the die temperature by means of a sensible element integrated in the die. the device switch-off when the junction temperature reaches 165c (typ. value) with 15c hysteresis (typ. value). 1 10 100 0.1 1 10 cen [nf] tdelay [ m s]
13/23 l6206 application information a typical application using l6206 is shown in fig. 12. typical component values for the application are shown in table 2. a high quality ceramic capacitor in the range of 100 to 200 nf should be placed between the power pins (vs a and vs b ) and ground near the l6206 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. the capacitors connected from the en a /ocd a and en b /ocd b nodes to ground set the shut down time for the brgidge a and bridge b respectively when an over current is detected (see overcurrent protection). the two current sources (sense a and sense b ) should be connected to power ground with a trace length as short as possible in the layout. to increase noise immu- nity, unused logic pins are best connected to 5v (high logic level) or gnd (low logic level) (see pin descrip- tion). it is recommended to keep power ground and signal ground separated on pcb. table 2. component values for typical application figure 12. typical application c 1 100uf d 1 1n4148 c 2 100nf d 2 1n4148 c boot 220nf r cla 5k w c p 10nf r clb 5k w c ena 5.6nf r ena 100k w c enb 5.6nf r enb 100k w c ref 68nf r p 100 w c p c boot r p d 2 d 1 c 2 out1 a load a load b ocd a ocd b 1 5 21 18 19 8 16 out2 a gnd gnd gnd gnd progcl a out2 b out1 b vs a power ground signal ground + - vs 8-52v dc 4 vs b vcp vboot c 1 sense a 20 in1 a in2 a in1 a in2 a 2 6 7 9 en a en b c enb r enb r ena en a en b 23 in2 b 12 in1 b in2 b in1 b 11 14 24 17 3 15 22 sense b r cla 10 c ena progcl b 13 r clb d02in1344
l6206 14/23 paralleled operation the outputs of the l6206 can be paralleled to increase the output current capability or reduce the power dissi- pation in the device at a given current level. it must be noted, however, that the internal wire bond connections from the die to the power or sense pins of the package must carry current in both of the associated half bridges. when the two halves of one full bridge (for example out1 a and out2 a ) are connected in parallel, the peak current rating is not increased since the total current must still flow through one bond wire on the power supply or sense pin. in addition the over current detection senses the sum of the current in the upper devices of each bridge (a or b) so connecting the two halves of one bridge in parallel does not increase the over current detec- tion threshold. for most applications the recommended configuration is half bridge 1 of bridge a paralleled with the half bridge 1 of the bridge b, and the same for the half bridges 2 as shown in figure 13. the current in the two devices connected in parallel will share very well since the r ds(on) of the devices on the same die is well matched. when connected in this configuration the over current detection circuit, which senses the current in each bridge (a and b), will sense the current in upper devices connected in parallel independently and the sense circuit with the lowest threshold will trip first. with the enables connected in parallel, the first detection of an over current in either upper dmos device will turn of both bridges. assuming that the two dmos devices share the current equally, the resulting over current detection threshold will be twice the minimum threshold set by the resistors r cla or r clb in figure 13. it is recommended to use r cla = r clb . in this configuration the resulting bridge has the following characteristics. - equivalent device: full bridge - r ds(on) 0.15 w typ. value @ t j = 25c - 5.6a max rms load current - 11.2a max ocd threshold figure 13. parallel connection for higher current c p c boot r p d 2 d 1 c 2 out1 a load ocd a ocd b 1 5 21 18 19 8 16 out2 a gnd gnd gnd gnd progcl a out2 b out1 b vs a power ground signal ground + - vs 8-52v dc 4 vs b vcp vboot c 1 sense a 20 in2 in1 a in2 b 12 6 7 9 en a en b r en en 23 in1 b 11 in2 a in1 2 14 24 17 3 15 22 sense b r cla 10 c en progcl b 13 r clb d02in1364
15/23 l6206 to operate the device in parallel and maintain a lower over current threshold, half bridge 1 and the half bridge 2 of the bridge a can be connected in parallel and the same done for the bridge b as shown in figure 14. in this configuration, the peak current for each half bridge is still limited by the bond wires for the supply and sense pins so the dissipation in the device will be reduced, but the peak current rating is not increased. when connected in this configuration the over current detection circuit, senses the sum of the current in upper devices connected in parallel. with the enables connected in parallel, an over current will turn of both bridges. since the circuit senses the total current in the upper devices, the over current threshold is equal to the threshold set the resistor r cla or r clb in figure 14. r cla sets the threshold when outputs out1 a and out2 a are high and resistor r clb sets the threshold when outputs out1 b and out2 b are high. it is recommended to use r cla = r clb . in this configuration, the resulting bridge has the following characteristics. - equivalent device: full bridge - r ds(on) 0.15 w typ. value @ t j = 25c - 2.8a max rms load current - 5.6a max ocd threshold figure 14. parallel connection with lower overcurrent threshold c p c boot r p d 2 d 1 c 2 out1 a load ocd a ocd b 1 5 21 18 19 8 16 out2 a gnd gnd gnd gnd progcl a out2 b out1 b vs a power ground signal ground + - vs 8-52v dc 4 vs b vcp vboot c 1 sense a 20 in a in1 a in2 a 2 6 7 9 en a en b c en r en en 23 in2 b 12 in1 b in b 11 14 24 17 3 15 22 sense b r cla 10 progcl b 13 r clb d02in1361
l6206 16/23 it is also possible to parallel the four half bridges to obtain a simple half bridge as shown in fig. 15. in this configuration the, the over current threshold is equal to twice the minimum threshold set by the resistors r cla or r clb in figure 15. it is recommended to use r cla = r clb . the resulting half bridge has the following characteristics. - equivalent device: half bridge - r ds(on) 0.075 w typ. value @ t j = 25c - 5.6a max rms load current - 11.2a max ocd threshold figure 15. paralleling the four half bridges c p c boot r p d 2 d 1 c 2 out1 a load ocd a ocd b 1 5 21 18 19 8 16 out2 a gnd gnd gnd gnd progcl a out2 b out1 b vs a power ground signal ground + - vs 8-52v dc 4 vs b vcp vboot c 1 sense a 20 in in1 a in2 a 2 6 7 9 en a en b c en r en en 23 in2 b 12 in1 b 11 14 24 17 3 15 22 sense b r cla 10 progcl b 13 r clb d02in1365
17/23 l6206 output current capability and ic power dissipation in fig. 16 and fig. 17 are shown the approximate relation between the output current and the ic power dissipa- tion using pwm current control driving two loads, for two different driving types: C one full bridge on at a time (fig.16) in which only one load at a time is energized. C two full bridges on at the same time (fig.17) in which two loads at the same time are energized. for a given output current and driving type the power dissipated by the ic can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guar- antee a safe operating junction temperature (125c maximum). figure 16. ic power dissipation versus output current with one full bridge on at a time. figure 17. ic power dissipation versus output current with two full bridges on at the same time. thermal management in most applications the power dissipation in the ic is the main factor that sets the maximum current that can be de- liver by the device in a safe operating condition. therefore, it has to be taken into account very carefully. besides the available space on the pcb, the right package should be chosen considering the power dissipation. heat sinking can be achieved using copper on the pcb with proper area and thickness. figures 19, 20 and 21 show the junction-to- ambient thermal resistance values for the powerso36, powerdip24 and so24 packages. for instance, using a powerso package with copper slug soldered on a 1.5 mm copper thickness fr4 board with 6cm 2 dissipating footprint (copper thickness of 35m), the r th j-amb is about 35c/w. fig. 18 shows mount- ing methods for this package. using a multi-layer board with vias to a ground plane, thermal impedance can be reduced down to 15c/w. no pwm f sw = 30khz (slow decay) test conditions: supply voltage = 24v i a i b i out i out 0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 p d [w] i out [a] one full bridge on at a time no pwm f sw = 30khz (slow decay) test conditions: supply voltage = 24v i a i b i out i out 00.511.522.5 3 0 2 4 6 8 10 p d [w ] i out [a ] two full bridges on at the same time
l6206 18/23 figure 18. mounting the powerso package. figure 19. powerso36 junction-ambient thermal resistance versus on-board copper area. figure 20. powerdip24 junction-ambient thermal resistance versus on-board copper area. figure 21. so24 junction-ambient thermal resistance versus on-board copper area. slug soldered to pcb with dissipating area slug soldered to pcb with dissipating area plus ground layer slug soldered to pcb with dissipating area plus ground layer contacted through via holes 13 18 23 28 33 38 43 12345678910111213 without ground layer with ground layer with ground layer+16 via holes sq. cm oc / w on-board copper area 39 40 41 42 43 44 45 46 47 48 49 1 2 3 4 5 6 7 8 9 101112 copper area is on bottom side copper area is on top side s q. cm oc / w on-board copper area 48 50 52 54 56 58 60 62 64 66 68 123456789101112 copper area is on top side sq. cm oc / w on-board copper area
19/23 l6206 figure 22. typical quiescent current vs. supply voltage figure 23. normalized typical quiescent current vs. switching frequency figure 24. typical low-side r ds(on) vs. supply voltage figure 25. typical high-side rds(on) vs. supply voltage figure 26. normalized r ds(on) vs.junction temperature (typical value) figure 27. typical drain-source diode forward on characteristic 4.6 4.8 5.0 5.2 5.4 5.6 0 102030405060 iq [ma] v s [v] f sw = 1khz t j = 25c t j = 85c t j = 125c 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 0 20406080100 iq / (iq @ 1 khz) f sw [khz] 0.276 0.280 0.284 0.288 0.292 0.296 0.300 0 5 10 15 20 25 30 r ds(on) [ w ] v s [v] t j = 25c 0.336 0.340 0.344 0.348 0.352 0.356 0.360 0.364 0.368 0.372 0.376 0.380 0 5 10 15 20 25 30 r ds(on) [ w ] v s [v] t j = 25c 0.8 1.0 1.2 1.4 1.6 1.8 0 20406080100120140 r ds(on) / (r ds(on) @ 25 c) tj [c] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 700 800 900 1000 1100 1200 1300 i sd [a] v sd [mv] t j = 25c
l6206 20/23 dim. mm inch min. typ. max. min. typ. max. a 3.60 0.141 a1 0.10 0.30 0.004 0.012 a2 3.30 0.130 a3 0 0.10 0 0.004 b 0.22 0.38 0.008 0.015 c 0.23 0.32 0.009 0.012 d (1) 15.80 16.00 0.622 0.630 d1 9.40 9.80 0.370 0.385 e 13.90 14.50 0.547 0.570 e 0.65 0.0256 e3 11.05 0.435 e1 (1) 10.90 11.10 0.429 0.437 e2 2.90 0.114 e3 5.80 6.20 0.228 0.244 e4 2.90 3.20 0.114 0.126 g 0 0.10 0 0.004 h 15.50 15.90 0.610 0.626 h 1.10 0.043 l 0.80 1.10 0.031 0.043 n10 (max.) s8 (max.) (1): "d" and "e1" do not include mold flash or protrusions - mold flash or protrusions shall not exceed 0.15mm (0.006 inch) - critical dimensions are "a3", "e" and "g". powerso36 e a2 a e a1 pso36mec detail a d 118 19 36 e1 e2 h x 45? detail a lead slug a3 s gage plane 0.35 l detail b detail b (coplanarity) gc - c - seating plane e3 c n n ? m 0.12 ab b b a h e3 d1 bottom view outline and mechanical data
21/23 l6206 dim. mm inch min. typ. max. min. typ. max. a 4.320 0.170 a1 0.380 0.015 a2 3.300 0.130 b 0.410 0.460 0.510 0.016 0.018 0.020 b1 1.400 1.520 1.650 0.055 0.060 0.065 c 0.200 0.250 0.300 0.008 0.010 0.012 d 31.62 31.75 31.88 1.245 1.250 1.255 e 7.620 8.260 0.300 0.325 e 2.54 0.100 e1 6.350 6.600 6.860 0.250 0.260 0.270 e1 7.620 0.300 l 3.180 3.430 0.125 0.135 m 0? min, 15? max. powerdip 24 a1 b e b1 d 13 12 24 1 l a e1 a2 c e1 sdip24l m outline and mechanical data
l6206 22/23 outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.200 c 0.23 0.32 0.009 0.013 d (1) 15.20 15.60 0.598 0.614 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.0 10.65 0.394 0.419 h 0.25 0;75 0.010 0.030 l 0.40 1.27 0.016 0.050 k 0? (min.), 8? (max.) ddd 0.10 0.004 (1) d dimension does not include mold flash, protusions or gate burrs. mold flash, protusions or gate burrs shall not exceed 0.15mm per side. so24 0070769 c weight: 0.60gr
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